Time memory cell VLSI and a high-speed serial interface : Submitted to the first workshop on electronics for LHC experiments,Lisbon,Porutogal,Sept.11-15,1995 / Y.Arai,M.Ikeno,H.Shirasu,T.Emura, 1995. - 5 p. - Текст : непосредственный.
Arai Y. Development of a CMOS time memory cell VLSI and a CAMAC module with 0.5 ns resolution : Submitted to the IEEE nuclear science symp., Nov.5-9, 1991, Santa Fe (NM) / Y.Arai,M.Ikeno,T.Matsumura, 1992. - 5 p. - Текст : непосредственный.
A VME 32 ch pipeline TDC module with TMC LSIs / H.Shirasu,Y.Arai,M.Ikeno и др., 1995. - 5 p. - Текст : непосредственный.
Arai Y. A 64-ch time Memory Cell Module with a DSP and a VME interface : Submitted to the IEEE nuclear science symp.,San Francisco(Ca),Nov.2-6 1993 / Y.Arai,M.Ikeno, 1993. - 6 p. - Текст : непосредственный.
Time memory cell VLSI for the PHENIX drift chamber : Submitted to the 1997 IEEE nuclear science symp.,Albuquerque,Nov.9-15,1997 / Y.Arai,M.Ikeno,M.Sagara,T.Emura, 1997. - 5 p. - Текст : непосредственный.
Arai Y. A time digitizer CMOS gate-array with a 250 ps time resolution : To be published in IEEE journal of solid-state circuits / Y.Arai,M.Ikeno, 1995. - 17 p. - Текст : непосредственный.
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