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621.3.049.771.14-/S11-585647
Sachdev, M. Defect-oriented testing for nano-metric CMOS VLSI circuits / M. Sachdev, J. P. Gyvez. - Electronic text data. - Boston, Ma : Springer, 2007. - (Frontiers in electronic testing, ISSN 0929-1296 ; 34). - URL: http://dx.doi.org/10.1007/0-387-46547-2. - ISBN 0-387-46547-2.

ГРНТИ	УДК
47.33.31	621.3.049.771.14-048.24

Рубрики:
Интегральные схемы большие -- Технический контроль

Доп. точки доступа:
Gyvez, J.P.
SpringerLink (Online service)
Экз-ры полностью 621.3.049.771.14-/S11-585647
http://dx.doi.org/10.1007/0-387-46547-2

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Bertacco V. Scalable hardware verification with symbolic simulation / V. Bertacco, 2006 r=on-line.Verification methodology manual for systemverilog / J. Bergeron [et al.], 2006 r=on-line.Mintz M. Hardware verification with C++ : a practitioner's handbook / M. Mintz, R. Ekendahl, 2006 r=on-line.Bergeron J. Writing testbenches using system verilog / J. Bergeron, 2006 r=on-line.DasGupta P. A roadmap for formal property verification / P. DasGupta, 2006 r=on-line.Sachdev M. Defect-oriented testing for nano-metric CMOS VLSI circuits / M. Sachdev, J. P. Gyvez, 2007 r=on-line.Carter H.B. Metric- driven design verification : an engineer's and executive's guide to first pass success / H. B. Carter, S. Hemmady, 2007 r=on-line.Wiemann A. Standardized functional verification / A. Wiemann, 2007 r=on-line.Mintz M. Hardware verification with systemverilog : an object-oriented framework / M. Mintz, R. Ekendahl, 2007 r=on-line.Spear C. System verilog for verification : a guide to learning the testbench language features / C. Spear, 2008 r=on-line.Boule M. Generating hardware assertion checkers : for hardware verification, emulation, Ppst-fabrication debugging and on-line monitoring / M. Boule, Z. Zilic, 2008 r=on-line.Исследование и разработка универсальных методов тестирования IP блоков систем на кристалле на базе микропроцессорных ядер : автореф. дис. .. канд. техн. наук : 05.27.01 / А. А. Алексеев, 2012. - 28 с. - Текст : непосредственный.System-level validation: high-level modeling and directed test generation techniques / M. Chen [et al.], 2013. - XVII, 247 p. - Текст : непосредственный.Валидация на системном уровне. Высокоуровневое моделирование и управление тестированием / М. Чэнь [и др.] ; пер. с англ. Е. Б. Махияновой , под ред. А. Н. Ланцева , 2014. - 294 с. - Текст : непосредственный.Liu X. Trace-Based Post-Silicon Validation for VLSI Circuits / X. Liu, Q. Xu, 2014 r=on-line.Bhushan M. Microelectronic Test Structures for CMOS Technology / by Manjul Bhushan, Mark B. Ketchen., 2011 r=on-line (Введено оглавление). - Текст : электронный.Смирнов, Константин Константинович. Автоматизация проектирования функциональных тестов для технологической подготовки производства интегральных микросхем : специальность 05.13.12 - Системы автоматизации проектирования (в технических системах) (технические науки) : автореферат диссертации на соискание ученой степени кандидата технических наук / Смирнов Константин Константинович, 2021. - 16 с. - Текст : непосредственный.

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